1. Field of the Invention
The present invention relates to a decoder circuit used in a driving circuit of a liquid crystal display panel or the like. More particularly, the present invention relates to a decoder circuit that is able to selectively output a voltage from gray-scale voltages corresponding to the number of gray-scale levels in input digital data by generating voltages for interpolating reference voltages smaller in the number of the gray-scale levels.
2. Description of Related Art
A decoder circuit used in a driving circuit of a liquid crystal display panel converts digital image data input externally into an analog signal to supply to a signal line of the liquid crystal display panel. If digital data input to the decoder circuit is 10 bits, for example, such decoder circuit must be able to generate an output signal of 210 (1024) ways of voltage levels.
A decoder circuit in general is configured to select one reference voltage corresponding to input digital data from several reference voltages generated by dividing between highest-level and lowest-level reference voltages by a ladder resistance and supply the selected reference voltage to a signal line of a liquid crystal panel via a buffer amplifier (voltage follower). However, with progress in growth of a number of gray-scale levels and higher-resolution of liquid crystal displays, there is a problem in the configuration to generate reference voltages corresponding to the number of all gray-scale levels in the input digital data by a ladder resistance of increasing the size of a decoder circuit and driving circuit including the decoder circuit.
Therefore, a decoder circuit is suggested for generating reference voltages smaller in the number of all gray-scales in digital data by a ladder resistance and generating lacking gray-scale voltages by interpolating between the reference voltages by an operational amplifier (see for example Japanese Unexamined Patent Application Publication No. 2002-43944). A configuration example of such decoder circuit is shown in FIG. 10.
A decoder circuit 733 in FIG. 10 inputs 10 bits of image data Dk and selects an output voltage corresponding to the input image data Dk from 1024 ways of voltage levels. The decoder circuit 733 inputs 28+1 of reference voltages VR0 to VR256, which is 257 gray-scales, that are generated by a reference voltage generation circuit not shown. The decoder circuit 733 can generate 210 which is 1024 levels of output voltages by interpolating between the reference voltages by an operational amplifier 137. In the explanation below, the reference voltage VR0 is assumed to be a reference voltage of a minimum voltage level, where the voltage level increases as the subscript increases, and the reference voltage VR256 is assumed to be a reference voltage of a maximum voltage level.
In FIG. 10, a D/A converter (DAC) 134 inputs upper 8 bits (bit 9 to bit 2) of the image data Dk and 257 levels of reference voltages and selects one voltage from the 257 levels of reference voltages according to the upper 8 bits of the image data Dk to output. As with the DAC 134, a DAC 135 also selects one voltage from the 257 levels of reference voltages according to the upper 8 bits of the image data Dk to output. Note that a decode logic for the DACs 134 and 135 is configured so that the DACs 134 and 135 select two adjacent reference voltages, for example VR0 and VR1.
Output voltages VD1 and VD2 of the DACs 134 and 135 are input to a selection circuit 136. The selection circuit 136 selects an input voltage from VD1 and VD2 to be supplied to four input terminals of the operational amplifier 137, which is described later. The selection circuit 136 includes six switches SW1 to SW6. Switching ON/OFF of the switches SW1 to SW6 is determined by lower 2 bits of the image data Dk. Note that the switches SW1 and SW4 operate complementally, meaning that when one of the switches is ON, another is OFF. By such operation, the input voltage to an input terminal VIN1 is determined to be VD1 or VD2. Likewise, by the complemented operation of the switches SW2 and SW5, the input voltage to an input terminal VIN2 is determined to be VD1 or VD2. Furthermore, by the complemented operation of the switches SW3 and SW6, the input voltage to an input terminal VIN3 is determined to be VD1 or VD2.
The operational amplifier 137 includes four input differential pairs. The operational amplifier 137 includes a negative feedback line for connecting an output terminal with an inverting input terminal and operates as a voltage follower. Note that among the four inverting input terminals of the operational amplifier 137, two terminals are short-circuited and a common signal is input to these two terminals. By such configuration, according to the combination of voltages input to the input terminals VIN1 to VIN3, the operational amplifier 137 outputs an output voltage VSk, where the output voltage VSk is selected from two adjacent reference voltages VRi and VRi+1 and three interpolated voltages obtained from a linear interpolation between VRi and VRi+1. The output voltage VSk from the operational amplifier 137 can be represented by the following formula (1).VSk=(VIN1+VI2+2×VIN3)/4  (1)
A relationship between the 257 levels of reference voltages VR0 to VR256 and the output voltage VSk generated from these reference voltages is shown in the table of FIG. 11. As an example, a case is considered in which a gray-scale level of the image data Dk is 0, meaning that the image data Dk is “0000000000”. In this case, the DAC 134 selects VR0 and the DAC 135 selects VR1. Moreover, the selection circuit 136 selects VD1 to all of VIN1 to VIN3. Then the output voltage VSk from the operational amplifier 137 is (VR0+VR0+2VR0)/4=VR0.
Furthermore, if the gray-scale level of the image data Dk is 1, meaning the image data Dk is “0000000001”, the DAC 134 selects VR0 and the DAC 135 selects VR1. Moreover, the selection circuit 136 selects VD1 for the VIN1 and VIN3 and selects VD2 for the VIN2. Then the output voltage VSk from the operational amplifier 137 is (3VR0+VR1)/4.
A decoder circuit as shown in FIG. 10 for generating an interpolated voltage using an operational amplifier has a characteristic that a voltage variation characteristic in a transition period until a gray-scale voltage output from the decoder circuit converges to a predetermined voltage level largely differs depending on a voltage level of the gray-scale voltage when a gray-scale level of the input image data Dk changes exceeding a range generable from combinations of same reference voltages. For example, as for the decoder 733 of FIG. 10, a voltage variation characteristic fluctuates in a transition period until a gray-scale voltage output from the decoder circuit 733 converges to a predetermined voltage level, depending on the selection of the input differential pairs connected with outputs of the DACs 134 and 135.
Accordingly, the present inventor has recognized that in a transition period until a gray-scale voltage output from the decoder circuit converges to a predetermined voltage level, a deviation of a voltage difference between two adjacent gray-scale levels from the predetermined voltage difference is large. Furthermore, the present inventor has also discovered that due to this problem, the time taken for the gray-scale voltage output from the decoder circuit to converge to a predetermined level is long. The problems for the decoder circuit are described hereinafter in detail with reference to FIGS. 12 and 13.
In the decoder circuit 733 shown in FIG. 10, the number of input differential pairs connected with the output of the DACs 134 and 135 varies according to the voltage level of the output voltage VSk. To be more specific, when image data has a gray-scale level k (for example gray-scale level 0), four input differential pairs included in the operational amplifier 137 are connected with the output of the DAC 134 while no input differential pair is connected with the output of the DAC 135. When the image data is gray-scale level k+1 (for example gray-scale level 1), three input differential pairs are connected with the output of the DAC 134 and one input differential pair is connected with the output of the DAC 135. When the image data is gray-scale level k+2 (for example gray-scale level 2), two input differential pairs are connected with the output of the DAC 134 and two input differential pairs are connected with the output of the DAC 135. When the image data is gray-scale level k+3 (for example gray-scale level 3), one input differential pair is connected with the output of the DAC 134 and three input differential pairs are connected with the output of the DAC 135. When the image data is gray-scale level k+4 (for example gray-scale level 4), no input differential pair is connected with the output of the DAC 134 four input differential pairs are connected with the and output of the DAC 135.
As described above, in the decoder circuit 733, the number of input differential pairs connected with the output of the DACs 134 and 135 fluctuates according to the voltage level of the output voltage VSk. That is, by the voltage level (gray-scale level) selected by the decoder circuit 733, load capacitances for the DACs 134 and 135 change. Therefore, by a difference in combinations of the input differential pairs connected with the output of the DACs 134 and 135, voltage variation characteristics for VD1 and VD2 largely differ when the reference voltage selected by the DAC 134 or 135 changes. Therefore, a variation characteristic of the output voltage VSk from the operational amplifier 137 when the reference voltage selected by the DAC 134 or 135 changes depending on the combination of the input differential pairs connected with the output from the DACs 134 and 135.
FIG. 12 is a graph showing an example of voltage levels of the input signals VD1 and VD2 for the operational amplifier 137 and the output signal VSk from the operational amplifier 137. To be more specific, FIG. 12 shows voltage changes when VD1 and VD2 transit from near voltage level A to voltage level B by a change in the reference voltage selected by the DAC 134 or 135.
In FIG. 12, VD1(n+1) is an output voltage of the DAC 134 in case of gray-scale level n+1 and VD2(n+1) is an output voltage of the DAC 135 in case of gray-scale level n+1. The voltage level of the reference voltage selected by the DAC 135 is higher than the reference voltage selected by the DAC 134, and in a state where an output voltage converges, the relationship is represented as VD1(n+1)<VD2(n+1). Furthermore, in case of gray-scale level n+1, suppose that three input differential pairs are connected with the output of the DAC 134 and one input differential pair is connected with the output of the DAC 135. In such case, the output VD2(n+1) from the DAC 135 having a small load capacitance converges to a predetermined voltage level (near voltage B) faster than the output VD1(n+1) of the DAC 134. Therefore, in the transition period until the voltage levels of VD(n+1) and VD1(n+2) converge, the voltage levels of VD1(n+1) and VD2(n+1) are reversed to be (VD1(n+1)>VD2(n+1)) and a voltage difference between them increases.
On the other hand, in FIG. 12, VD1(n+2) is an output voltage of the DAC 134 in case of gray-scale level n+2 and VD2(n+2) is an output voltage of the DAC 135 in case of gray-scale level n+2. In case of gray-scale level n+2, suppose that two input differential pairs are connected with the output of the DAC 134 and two input differential pairs are connected with the output of the DAC 135. In such case, the load capacitances connected with the outputs of the DACs 134 and 135 are equivalent. Therefore convergence speeds of VD1(n+2) and VD2(n+2) are almost equal and are almost middle between a convergence speed of VD1(n+1) and that of VD2(n+1).
As described above, due to the difference in the voltage variation characteristics of VD1 and VD2 which are input signals to the operational amplifier 137, as shown in FIG. 12, a variation characteristic of the output VSk(n+1) in case of gray-scale level n+1 differs from a variation characteristic of the output VSk(n+2) in case of gray-scale level n+2. FIG. 13 illustrates a voltage difference between two adjacent gray-scale levels when driving a liquid crystal display panel (panel load) by VSk(n+1) and VSk(n+2) shown in FIG. 12. In FIG. 13, the voltage difference between two adjacent gray-scale levels changes from voltage C to voltage D. However the time taken for the voltage difference converges to a predetermined voltage difference (voltage D) is long and a deviance of the voltage difference between two adjacent gray-scale levels from the predetermined voltage difference (voltage D) is large in a transition period. These phenomena are particularly apparent in a far end of a panel load.